A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
The pattern is transferred onto several successive resist layers on the substrate in order to build up a multi-layer structure with the pattern throughout its thickness. It is therefore important to ensure that the pattern in any given layer is exactly aligned with the pattern in the previous layer. Specifically, a substrate is covered with a layer of resist and then the pattern is transferred onto that layer (by a process known as “exposure”). The layer is then treated post-exposure such that the resist is removed except where the pattern was exposed. A subsequent layer of resist is then applied and the pattern transferred/exposed again and treated post-exposure again. This happens several tens of times, depending on the resist and the pattern. Each time a new resist layer is to be exposed, the pattern must be carefully aligned with the pattern of the previous resist layer in order to have a well-defined overall pattern at the end of the series of exposures and post-exposure treatments. The way that successive patterned layers are aligned is by having alignment marks in the layer, these alignment marks being detectable by an alignment beam that is projected by the projection system before the exposure beam is projected to apply the pattern. In order to leave as much space as possible on the substrate for the exposed pattern, the alignment marks are positioned in scribe lanes, which is the part of the substrate that will be sawn to separate the substrate into individual ICs, for example. Alignment marks have, in the past, taken the form of stacked (in several or all the layers) copper areas alternating with dielectric areas.
As lithographic techniques improve and smaller patterns are possible, smaller ICs are also possible and so the area between the scribe lanes decreases. If the scribe lanes stay the same size while the “usable” area between them gets smaller, the ratio of unusable substrate to usable substrate increases, reducing efficiency of the substrate use. The use of relatively large copper areas in the alignment marks in the scribe lanes means that the size of the scribe lanes is difficult to decrease and so inefficient use of substrate space is inevitable. Furthermore users of lithographic apparatuses use the scribe lanes and other non-patterned areas for other non-pattern marks and targets. Smaller or more re-usable alignment marks, are thus desirable.
Alignment marks that are used in the state of the art contain large (e.g. copper) structures (i.e. large compared to the typical device dimensions). For processing reasons, the alignment mark should resemble the device/product dimensions to guarantee alignment accuracy. Therefore, a sub-segmentation is carried out to the large areas (e.g. structures 10 in FIG. 2) inside the mark. For example, the alignment mark consists of copper areas alternated by dielectric areas. If there is sub-segmentation of larger alignment marks to save space, the marks become semi-transparent to certain wavelengths (such as those used for alignment). There can therefore not be “mark-stacking”, as marks at the bottom of the stack will have an effect on the diffraction of the radiation beam applied to it. However, mark stacking is a preferred method in the prior art because previous marks do not in that case have to be removed and time and machinery is saved. Furthermore, with mark stacking, marks can be reapplied to the same space, thus saving space over the length of the multiple exposure process.